Have you ever had a duty-cycle resolution issue in your digitally controlled power supply?

In a digital pulse width modulation (DPWM)-controlled power supply, the duty-cycle adjustment is not continuous, but has a minimum step. This is one significant difference between digital control and analog control.

In order to really understand the resolution issue, let’s look at the exaggerated DPWM waveform in Figure 1.

Figure 1 An exaggerated DPWM waveform where the DPWM is acting as the output by comparing its clock counter with a preset comparison value. Source: Texas Instruments

DPWM is acting as the output by comparing its clock counter with a preset comparison value; when the counter equals the comparison value, it will generate a trigger signal, and flip the PWM outputs. When you adjust the comparison to different values, the flipping edge will act earlier or later. Because the counter value can be the only integer, the minimum adjustment step of the duty cycle is expressed by Equation 1:

Oscillation caused by low duty-cycle resolution

The duty-cycle resolution of DPWM brings a disturbance to power-supply control. If the duty-cycle resolution is too low, it may bring limit cycle oscillations (LCOs) to the control loop and cause output voltage ripple. This problem is more serious in high-switching-frequency systems.

Let’s take a 48-V to 5-V synchronous buck converter as an example, as shown in Figure 2.

Figure 2 A 48-V to 5-V synchronous buck converter example. Source: Texas Instruments

Assuming a 500-kHz switching frequency when using 120-MHz PWM frequency, recalling Equation 1, the minimum duty-cycle step is . The minimum duty-cycle adjustment brings the voltage difference with , which means 4% voltage ripples of the output, shown in Figure 3. This is obviously unacceptable.

Figure 3 A low-resolution duty cycle causes output voltage ripple. Source: Texas Instruments

Increase duty-cycle resolution

The most direct way to resolve this duty-cycle resolution issue is to use high-resolution PWM (HRPWM). HRPWM is a powerful peripheral that can reduce the adjustment step significantly—to the 10ps level—but it is typically only available in high-performance MCUs, which may be too powerful or expensive for the design.

Is there a simple method to resolve the duty-cycle resolution issue without extra cost? Can you increase the duty-cycle resolution by using software, or an algorithm?

Looking again at the DPWM waveform, the duty cycle is generated by two variables: the comparison value and the period value, which Equation 2 calculates as:

The common method of adjusting the duty cycle is changing the comparison value and keeping the ‘Period’ value in constant; in other words, the buck converter is operating in fixed switching frequency. What happens if you adjust the duty-cycle by varying the switching frequency? Mostly, a small variation of the switching frequency is not harmful but helpful to power converters, it will reduce the electromagnetic interference and help to pass the EMI regulations.

If you keep the comparison value unchanged, but adjust one count to the period value, how much is the duty-cycle variation? Is it larger or smaller than adjusting the comparison value? Please look into the Equation 3:

Keeping in mind that, the duty-cycle variation by adjusting the comparison value is , because D is always smaller than 1, and  is nearly equal to , you can see that  will be always smaller than .

Which means, adjusting the period value will generate smaller variation to the duty-cycle than adjusting the comparison value.  The improvement is more significant when the duty cycle is much smaller than 1. If you point out the duty-cycle values on one numerical axis with varying the period value, you will clearly see that, when you adding the period value with fixed comparison value, the duty cycle will reduce with a smaller step, as shown in Figure 4.

Figure 4 Duty-cycle values when varying both period and comparison. Source: Texas Instruments

Varying the frequency

Based on the analysis above, it is possible to generate a higher resolution by adjusting the period value. But, in power converter, the switching frequency generally can’t vary much, otherwise the magnetic component design will become very challenge. So, the next question is, how to generate the expected duty cycle with the combination of these two variables?

The method is, first, decided the comparison value with a preset period value, and then, finetune the period value to get the closed duty cycle. The fine tune process either can by increasing the period value with the larger the comparison value, or by reducing the period value with the smaller the comparison value. Figure 5 shows the flowchart of the software by increasing the period value with the larger comparison value, the decreasing method will be similar to this, just need reverse the calculate direction.

Figure 5 Software flowchart for adjusting both the comparison and period values simultaneously. Source: Texas Instruments

At last, I need to figure out that, this software method is principally independent of HRPWM hardware technology, such as a micro-edge positioner. So it is applicable to a digital control loop with HRPWM peripherals same.

Improvement results

Let’s return to the example of the 48-V to 5-V synchronous buck converter in Figure 2. After adopting this software method, it’s possible to reduce the duty-cycle resolution too; the output voltage ripple drops tremendously to <40 mV, as shown in Figure 6. This is acceptable to most of the electrical appliance.

Figure 6 Improved output voltage ripple using the software method. Source: Texas Instruments

This method doesn’t need to use HRPWM to solve the duty-cycle resolution problem, but slightly increasing the duty-cycle resolution with a software algorithm can make your product more competitive by enabling the use of a low-end MCU.

Furthermore, this method is a purely mathematical algorithm; in other words, it is not limited to low-resolution PWM only but also works for HRPWM. So it can be used in some extremely high requirement conditions to further increase the duty-cycle resolution with HRPWM.

Desheng Guo is a system engineer at Texas Instruments, where he is responsible for developing power solutions as part of the power delivery industrial segment. He created multiple reference designs and is familiar with AC-DC power supply, digital control, and GaN products. He received a master’s degree from the Harbin Institute of Technology in power electronics in 2007, and previously worked for Huawei Technology and Delta Electronics.

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