Chip startup Efficient Computer Corp. exited stealth mode in 2024 with a $16 million seed funding round with the announcement of its first computer processor, the E0 system-on-chip (SoC) for prototyping and evaluation, claiming “unprecedented energy efficiency.” The spinout from Carnegie Mellon University is now releasing its Electron E1 general-purpose processor to developers, together with its effcc Compiler.
Efficient Computer taped out its first silicon, the E0 prototype SoC, in early 2024, built on GlobalFoundaries’ 22-nm process (22FDX platform), and is now launching the E1 processor through its Early Access Silicon Program. The E1 SoC is also available as an integratable IP that customer partners can integrate into their SoCs.
Aimed at edge, embedded, and AI product applications, the new computer architecture and software stack offers a new approach to general-purpose computation that eliminates the energy overheads in existing general-purpose processor architectures.
Claiming up to 100× higher energy efficiency than general-purpose CPUs and 1,000× lower power than today’s GPUs, the ultra-energy-efficient Electron E1 architecture targets applications in which battery life, latency, and deployment scale are critical, including industrial infrastructure, space systems, and defense systems. With its more efficient computing on-device, it enables smart edge devices with longer battery life and increased computing capabilities in applications that have power and maintenance challenges.
Thanks to the company’s reconfigurable spatial dataflow Fabric architecture, Efficient Computer has been able to achieve higher energy efficiency than low-power CPUs. Compared with traditional von Neumann processors that consume more energy moving data between memory and compute cores, the spatial dataflow architecture executes general-purpose code, eliminating the need for costly step-by-step computation, the company said.
Comparison of a traditional processor and Fabric processor architecture (Source: Efficient Computer Corp.)
The result is a new category of general-purpose processors that are orders of magnitude more efficient than anything else in the market, said Brandon Lucia, Efficient Computer’s CEO and co-founder. “We have the efficiency of a dedicated fixed-function accelerator and the programmability of a general-purpose CPU.”
The company calls the Fabric processor architecture a paradigm shift, providing reconfigurable hardware at a compile time that has up to 99% lower DC power without compromising performance. Creating a new category of ultra-low-energy and high-performance processors, it also opens the door to entirely new categories of applications using the E1 and effcc Compiler, Lucia said.
“No one has ever seen a processor that can do this kind of variety of general-purpose computing tasks, including AI but also all the computation that goes around AI: digital-signal processing, analytics, graph computations, encryption, and compression,” he said.
The Fabric architecture
The research behind the Fabric architecture started about 10 years ago at Carnegie Mellon University, where the co-founder group, including Lucia, started to work on answering the fundamental question: Why are CPUs so inefficient with their energy?
After years of application-level studies trying to understand where the energy goes, the group arrived at the spatial dataflow architecture.
“This architecture doesn’t look anything like a CPU,” Lucia said. “For example, we don’t have a register file and an instruction fetch and decode unit that looks anything like a CPU’s instruction fetch and decode unit.
“In a CPU, every single cycle grabs a new instruction from the memory and puts it through the fetching unit and then pulls operands into the register file,” he added. Those kinds of overhead plus internal components and pipeline reconfiguration logic consume a majority of the energy, but “none of that energy goes into actually doing the arithmetic that you ask the computers to do.
“Instead of time-sharing internal components in a CPU, like typical CPUs have done forever in the execution pipelines that have looked the same since 1959, we spatially array the instructions in the program across the grid of processing elements or tiles, instead of laying it out one instruction at a time in a shared pipeline,” Lucia said.
E1 processor block diagram (Source: Efficient Computer Corp.)
However, this Fabric architecture design takes up more area than a compact CPU design. Lucia said it is an acceptable amount of area for the “disproportionate” gain in energy. “There is a small incremental increase in area for a disproportionately orders-of-magnitude increase in energy efficiency, and you get a big performance boost to boot.
“We are often 5×, 10×, and, in some cases, tens of times faster than comparable CPUs, especially if you normalize for power,” he added. “So that’s a huge win.”
This is thanks to the use of parallelism in the design. “We’re decomposing a program into its instructions and then mapping them spatially in parallel across hardware elements, which is unlike what most CPUs do, especially in the embedded space,” Lucia said.
Comparing Efficient Computer’s silicon with several competitive Arm Cortex-M33 processors used in common embedded applications, Lucia said the E1 uses between 10× to 50× less energy to run the same workload. He has also seen efficiency gains in the order of 150× when compared with devices optimized more for performance than efficiency.
Energy consumption comparison between E1 processor and Arm Cortex-M33 processors (Source: Efficient Computer Corp.)
Efficient Computer is releasing the E1 processor in a staged rollout up until volume production in 2026. “We will have a broad market volume product available in the second half of 2026, and we’re running an early access partnership program between now and then, fostering new partnerships and new customer relationships in the interim,” Lucia said.
A big part of the rollout is the effcc Compiler, which allows developers to use software written in familiar programming languages onto the Fabric processor architecture. Efficient Computer developed the compiler in conjunction with the chip development.
“Our compiler is such an important piece of our story and is so essential to the success of our hardware and to the success of our customers using our hardware,” Lucia said.
The compiler supports C, which is the Swiss-Army-Knife language for all embedded systems programming, and early support for C++, Lucia said. “We have a roadmap for support of other general-purpose languages in the near term, including, for example, Rust. We also have support for machine-learning models that are in the embedded-friendly TensorFlow Lite [TFLite], and we have broad support for and will soon have support for PyTorch and ONNX models as well.”
The effcc Compiler will support popular languages, such as C, C++, and TFLite, libraries, and frameworks. (Source: Efficient Computer Corp.)
E1 specifications and use cases
The E1 processor, featuring a low-power RISC-V scalar core, offers ultra low power (hundreds of microwatts) and energy efficiency up to 1 TOPS/W. It delivers 6 GOPS at low voltage (25-MHz Fabric/75-MHz memory) and 18 to 24 GOPS at high voltage (75- to 100-MHz Fabric/225- to 300-MHz memory). It also features ultra-low-power on-chip memory and storage with 4 MB of nonvolatile memory (MRAM) with DMA support, 3 MB of ultra-low-power SRAM, and 128 kB (8 kB/bank) of ultra-low-power cache.
The Fabric processor also features an on-board clock and power management and packs plenty of peripherals, including 6× QSPI, 6× UART, 6× SPI, and 6× I2C, as well as 72× GPIOs and 1× RTC. It is housed in a standard BGA package.
By using spatial dataflow between instructions, the Fabric processor improves performance and eliminates wasted energy, opening up new use cases for real-time processing and intelligent decision-making directly at the source of data. Because it is a general-purpose solution, it can handle diverse algorithms required for infrastructure intelligence.
Battery-powered sensors and devices using the Electron E1 processor can operate for years, the company said, significantly reducing maintenance needs and enabling deployments with minimal manual management. For example, it enables real-time processing and intelligent decision-making directly at the source of data, which is critical for applications such as predictive maintenance in industrial environments, and opens up applications in environments that were previously inaccessible or cost-prohibitive.
These innovations make it possible to use so much less energy, Lucia said. For example, infrastructure sensing devices are monitoring a million kilometers of oil and gas pipelines or power lines, and they are very high-coverage remote sites where observability is extremely valuable for the bottom line, he explained.
But there are a lot of impediments today to enabling predictive maintenance at industrial sites or in infrastructure applications, including battery-powered devices that are going to last only a couple of weeks, due to sensors that use 4G/5G radios to send data to the cloud, consuming lots of energy quickly, or using higher-power-consumption CPUs to support these applications, as examples, Lucia said.
“For small batteries, you want these to last three to five years, and when you get to that point, it starts to make sense, because you’re not replacing batteries every three weeks for a million devices that you have deployed in your infrastructure,” he added.
“Now you get this new level of observability,” Lucia said. “The ability to draw insights on-device from the raw data with advanced signal processing and analytics using AI and machine-learning models is very exciting. If you decrease the energy consumption of everything that’s happening on the device, and you can provide better functionality, better observability, and better insights out of the data, now you’re getting more value.”
Availability of the Electron E1 programmable processor marks Efficient Computer’s first standalone hardware release and targets a range of applications, including industrial infrastructure, space systems, defense, wearables, and IoT. Sampling will be available through the company’s Early Access Silicon Program. Engineering support includes collaborative optimization, code tuning, and architecture guidance.
In addition, the effcc Compiler is available for download for the first time. It was previously available only via the company’s internal sandbox. The compiler can now be integrated into developers’ existing toolchains to compile and deploy code to the E1 hardware. It supports C and TFLite now, with ONNX, Embedded C++, CircuitPython, and Rust support coming later in 2025.
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