Rare-earth minerals are essential to the modern world, powering everything from smartphones and electric vehicles to defence systems and renewable energy technologies. Yet, as the global demand for these materials surges, so too does the risk of relying heavily on a single supplier. Today, China holds a dominant position in rare-earth mining and refining, leaving much of the world vulnerable to supply chain disruptions and geopolitical leverage.

What makes these minerals so difficult to replace, how has the West responded to this strategic dependency, and could recent research from the University of Minnesota mark the beginning of a post-rare-earth era?

The challenge with chiplet design

Chiplets are increasingly viewed as the next major step in semiconductor design, promising smaller, more capable systems by integrating multiple dies into a single package. Instead of manufacturing one large, complex chip, engineers can design several smaller dies and combine them to create a high-performance system-on-package. This approach offers benefits in scalability, cost efficiency, and performance, particularly as monolithic chip designs become harder and more expensive to produce at advanced process nodes.

However, while the potential is enormous, chiplet technology faces several serious challenges that limit its widespread adoption, with one of the biggest obstacles being die-to-die communication. For a multi-die package to function effectively, its chiplets must exchange data rapidly and efficiently, but there is currently no universal standard for these interconnections. Each manufacturer tends to implement its own proprietary bus or interface, which makes interoperability between chiplets from different sources extremely difficult. In many cases, even minor mismatches in signalling, voltage, or timing can render a combination unusable without extensive redesign.

Manufacturing complexity is another significant issue that prevents their large-scale adoption. Integrating multiple dies onto a single substrate requires precision assembly, advanced packaging materials, and careful thermal management. The processes involved (such as 2.5D interposers and 3D stacking) demand manufacturing capabilities that only a few foundries currently possess. This makes production expensive and limits design flexibility, as each chiplet must be engineered to withstand both the mechanical and electrical stresses of integration.

Supply chain coordination also adds another layer of difficulty. A complete chiplet-based design might involve dies produced by several different companies, each using different fabrication technologies and design rules. Bringing these components together into a single, reliable package requires tight logistical and technical alignment, something the semiconductor industry is not yet structured to handle. Traditional manufacturing pipelines are optimised for discrete integrated circuits, where each chip is designed, fabricated, and tested independently.

Tenstorrent launches initiative targeting open chiplet design

Tenstorrent, the AI chip company led by renowned processor architect Jim Keller, has announced the launch of the Open Chiplet Atlas (OCA) ecosystem, an industry-wide initiative designed to standardise chiplet-based silicon design. Revealed at the company’s event in San Francisco, OCA aims to bring open, royalty-free specifications to one of the most complex and fragmented areas of semiconductor engineering.

Information from Tenstorrent’s announcement highlights that the Open Chiplet Atlas ecosystem is intended to give developers a clearer pathway for designing components around an open, shared roadmap rather than isolated vendor formats. The company states that long-term collaboration is central to the initiative, supporting a design environment where chiplet developers, toolchain providers and research organisations can reference a common blueprint when planning future architectures.

Industry collaboration behind the OCA ecosystem

More than fifty organisations are taking part in the effort, including LG, the Barcelona Supercomputing Centre, and Japan’s Rapidus, a government-backed chipmaking startup. Together, they intend to define a consistent framework that allows chiplets from multiple vendors to communicate and integrate seamlessly within a single package.

Tenstorrent indicates that interoperability is a core principle behind OCA, noting that chiplet designers often face hurdles when attempting to align interface assumptions across suppliers. Their materials suggest that open specifications may allow ecosystem participants to minimise bespoke point-to-point integration work, which has traditionally slowed early-stage prototyping and increased engineering overhead.

Technical layers and long-term roadmap

According to Wei-han Lien, Tenstorrent’s chief architect, the goal is to create “the foundation of trust and interoperability” required to unlock the potential of heterogeneous, multivendor chiplet systems. The group’s v0.7 draft specification has already been published for public review, outlining standards across five distinct layers: physical, transport, protocol, system, and software. These layers collectively form the basis for interoperability, ensuring that chiplets can be mixed and matched without extensive custom engineering.

• Architecture: A shared architectural model defining interoperability across five layers, covering physical signalling, transport behaviour, protocol rules, system interaction and software support.
• Harness: An open-source design framework that provides the common non-application logic for chiplets, allowing developers to focus on their functional blocks while maintaining compatibility with the wider ecosystem.
• Compliance: A programme aimed at verifying interoperability through pre-silicon checks and post-silicon validation, supported by a reference “Golden Chiplet” and community plugfests.

Additional detail from the company notes that the OCA’s layered approach is intended to help separate concerns between physical signalling, logical behaviour and software interaction. Tenstorrent references this as a way to ensure that future chiplets may be designed with predictable system requirements, supporting consistent behaviour even as vendors adopt different process technologies or packaging approaches.

The specifications are being released under a royalty-free license, which OCA members say will promote equal access and encourage collaboration among semiconductor companies, design houses, and foundries. By defining how chiplets interconnect, the ecosystem aims to streamline the design process and accelerate time-to-market for complex system-on-package products.

Tenstorrent’s release also emphasises that an open chiplet framework could support the growth of a broader supply ecosystem. The company states that reducing licensing barriers may encourage new entrants to participate in chiplet development, increasing access to complementary IP blocks and expanding the choice available to system integrators. Their comments further suggest that greater transparency in specifications could improve long-term maintainability for heterogeneous SoP designs.

Statements from Tenstorrent also indicate that the Open Chiplet Atlas is intended as a multi-year roadmap rather than a static specification. The company notes that future revisions may introduce expanded guidance for design automation tools, testing frameworks and validation procedures, helping organisations create chiplets that align with evolving workloads in AI acceleration, HPC and edge computing. This may support engineers seeking predictable adoption paths as chiplet-based architectures continue to mature.

Could this be the start of a new era in electronics?

The history of integrated circuits has always been tied to packaging. From the earliest dual-in-line packages (DIPs) to modern BGAs and TQFPs, discrete IC packages have enabled engineers to accelerate design cycles, scale complexity, and improve reliability. Yet, even these highly optimised packages are now approaching practical limits. As devices demand ever higher performance in smaller footprints, traditional approaches are increasingly constrained.

Chiplets undoubtedly represent the next evolution in electronics and high-tech designs. By combining multiple dies into a single package, engineers gain unprecedented flexibility. This modularity allows for smaller designs that still deliver higher performance and improved energy efficiency, while also opening the door to heterogeneous integration, where different process nodes or technologies can coexist in one system-on-package.

Looking further ahead, the concept of chiplets hints at even more radical possibilities. Techniques like chip-on-board, which directly bond dies onto PCBs, could evolve into large, complex assemblies where interconnects and wire-bonding replace traditional packaging entirely. In such systems, engineers might eventually integrate basic passive components, such as resistors and capacitors, directly into PCB traces, effectively extending lithography from the silicon die onto the board itself. This could dramatically reduce size, increase performance, and blur the distinction between IC design and PCB layout.

While these ideas remain largely experimental today, the trend is clear: modular, composable, and heterogeneous designs are set to dominate the next era of electronics. Chiplets offer a scalable path forward, providing both flexibility and performance in ways discrete packages cannot match. They are poised to reshape how engineers think about system design, integration, and manufacturing.

Time will determine just how far these concepts can go, but the direction is unmistakable. Just as discrete ICs transformed electronics in the late 20th century, chiplets, and the architectures they enable, seem set to define the future of integrated systems.