Marvell Technology, Inc. has claimed the industry’s first 2-nm 64 Gbits/s bi-directional die-to-die (D2D) interconnect, offering higher bandwidth and efficiency together with advanced power management for AI infrastructure. This will enable chip designers to boost the bandwidth and performance of next-generation XPUs (AI accelerators) while reducing power and silicon area.
The interface IP, delivering 32 Gbits/s of simultaneous two-way connectivity over a single wire, sets a new standard for performance, power efficiency, and resiliency to meet the scaling demands of next-generation data centers, Marvell said.
(Source: Marvell Technology, Inc.)
The 64 Gbits/s bi-directional D2D interface offers bandwidth density over 30 Tbits/s per mm, which is reported to be more than three times the bandwidth density of UCIe at equivalent speeds, and a minimal depth configuration that reduces compute die area requirements to 15% compared to conventional implementations.
The interface IP also claims the industry’s first in its class to feature advanced adaptive power management that automatically adjusts device activity to bursty data center traffic. This reduces interface power consumption by up to 75% with normal workloads and up to 42% during peak traffic periods, Marvell said.
Other features for enhanced performance and reliability include redundant lanes and automatic lane repair, which improve yield and reduce bit-error rates by eliminating weak links in the system. The interface IP is available in 2 nm and 3 nm.
Marvell also offers the application bridge, link layers, and physical interconnect for a complete solution stack to reduce time to market for next-generation XPUs.
The new 64 Gbits/s D2D interface technology builds on Marvell’s industry firsts in advanced process technologies, including the first infrastructure silicon company to announce a 2-nm platform. Marvell demonstrated working 2-nm silicon in March 2025, followed by the introduction of 2-nm custom SRAM technology.
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