In today’s information-driven society, there’s an ever-increasing preference to measure phenomena such as temperature, pressure, light, force, voltage and current. These measurements can be used in a plethora of products and systems, including medical diagnostic equipment, home heating, ventilation and air-conditioning systems, vehicle safety and charging systems, industrial automation, and test and measurement systems.

Many of these measurements require highly accurate signal-conditioning circuitry, which often includes an instrumentation amplifier (IA), whose purpose is to amplify differential signals while rejecting signals common to the inputs.

The most common issue when designing a circuit containing an IA is the misinterpretation of the boundary plot, also known as the common mode vs. output voltage, or V_CM vs. V_OUT plot. Misinterpreting the boundary plot can cause issues, including (but not limited to) signal distortion, clipping, and non-linearity.

Figure 1 depicts an example where the output of an IA such as the INA333 from Texas Instruments has distortion because the input signal violates the boundary plot (Figure 2).

Figure 1 Instrumentation amplifier output distortion is caused by V_CM vs. V_OUT violation. Source: Texas Instruments

Figure 2 This is how V_OUT is limited by V_CM. Source: Texas Instruments

This series about IAs will explain common- versus differential-mode signaling, basic operation of the traditional three-operational-amplifier (op amp) topology, and how to interpret and calculate the boundary plot.

This first installment will cover the common- versus differential-mode voltage and IA topologies, and show you how to derive the internal node equations and transfer function of a three-op-amp IA.

The IA topologies

While there are a variety of IA topologies, the traditional three-op-amp topology shown in Figure 3 is the most common and therefore will be the focus of this series. This topology has two stages: input and output. The input stage is made of two non-inverting amplifiers. The non-inverting amplifiers have high input impedance, which minimizes loading of the signal source.

Figure 3 This is how a traditional three-op-amp IA looks like. Source: Texas Instruments

The gain-setting resistor, R_G, allows you to select any gain within the operating region of the device (typically 1 V/V to 1,000 V/V). The output stage is a traditional difference amplifier. The ratio of R₂ to R₁ sets the gain of the difference amplifier. The balanced signal paths from the inputs to the output yield an excellent common-mode rejection ratio (CMRR). Finally, the output voltage, V_OUT, is referred to as the voltage applied to the reference pin, V_REF.

Even though three-op-amp IAs are the most popular topology, other topologies such as the two op amps offer unique benefits (Figure 4). This topology has high input impedance and single resistor-programmable gain. But since the signal path to the output for each input (V_+IN and V_-IN) is slightly different, this topology degrades CMRR performance, especially over frequency. Therefore, this type of IA is typically less expensive than the traditional three-op-amp topology.

Figure 4 The schematic shows a two-op-amp IA. Source: Texas Instruments

The IA shown in Figure 5 has a two-op-amp IA input stage. The third op amp, A3, is the output stage, which applies gain to the signal. Two external resistors set the gain. Because of the imbalanced signal paths, this topology also has degraded CMRR performance (<90dB). Therefore, devices with this topology are typically less expensive than traditional three-op-amp IAs.

Figure 5 A two-op-amp IA is shown with output gain stage. Source: Texas Instruments

While the aforementioned topologies are the most prevalent, there are several unique IAs, including current mirror, current feedback, and indirect current feedback.

Figure 6 depicts the current mirror topology. This type of IA is preferable because it enables an input common-mode range that extends to both supply voltage rails, also known as the rail-to-rail input. However, this benefit comes at the expense of bandwidth. Compared to two-op-amp IAs, this topology yields better CMRR performance (100dB or greater). Finally, this topology requires two external resistors to set the gain.

Figure 6 This is how current mirror topology looks like. Source: Texas Instruments

Figure 7 shows a simplified schematic of the current feedback topology. This topology leverages super-beta transistors (Q₁ and Q₂) to buffer input signal and forces it across the gain-setting resistor, R_G. The resulting current flows through R₁ and R₂, which create voltages at the outputs of A₁ and A₂. The difference amplifier, A₃, then rejects the common-mode signal.

Figure 7 Simplified schematic displays the current feedback topology. Source: Texas Instruments

This topology is advantageous because super-beta transistors yield a low input offset voltage, offset voltage drift, input bias current, and input noise (current and voltage).

Figure 8 depicts the simplified schematic of an indirect current feedback IA. This topology has two transconductance amplifiers (g_m1 and g_m2) and an integrator amplifier (g_m3). The differential input voltage is converted to a current (I_IN) by g_m1. The g_m2 stage converts the feedback voltage (V_FB-V_REF) into a current (I_FB). The integrator amplifier matches I_IN and I_FB by changing V_OUT, thereby adjusting V_FB.

Figure 8 This schematic highlights the indirect current feedback topology. Source: Texas Instruments

One significant difference when compared to the previous topology is the rejection of the common-mode signal. In current feedback IAs (and similar architectures), the common-mode signal is rejected by the output stage difference amplifier, A₃. Indirect current feedback IAs, however, reject the common-mode signal immediately at the input (g_m1). This provides excellent CMRR performance at DC over frequency and independent of gain.

CMRR performance does not degrade if there is impedance on the reference pin (unlike other traditional IAs). Finally, this topology requires two resistors to set the gain, which may deliver excellent performance across temperature if the resistors have well-matched drift behavior.

Common- and differential-mode voltage

The common-mode voltage is the average voltage at the inputs of a differential amplifier. A differential amplifier is any amplifier (including op amps, difference amplifiers and IAs) that amplifies a differential signal while rejecting the common-mode voltage.

The inverting terminal connects to a constant voltage, V_CM. Figure 9 depicts a more realistic definition of the input signal where two voltage sources represent V_D. Each source has half the magnitude of V_D. Performing Kirchhoff’s voltage law around the input loop proves that the two representations are equivalent.

Figure 9 The above schematic shows an alternate definition of common- and differential-mode voltages. Source: Texas Instruments

Three-op-amp IA analysis

Understanding the boundary plot requires an understanding of three-op-amp IA fundamentals. Figure 10 depicts a traditional three-op-amp IA with an input signal—with input and output nodes A1, A2 and A3 labeled.

Figure 10 A three-op-amp IA is shown with input signal and node labels. Source: Texas Instruments

Equation 1 depicts the overall transfer function of the circuit in Figure 10 and defines the gain of the input stage, G_IS, and the gain of the output stage, G_OS. Notice that the common-mode voltage, V_CM, does not appear in the output-voltage equation, because an ideal IA completely rejects common-mode input signals.

Noninverting amplifier input stage

Figure 11 depicts a simplified circuit that enables the derivation of node voltages V_IA1 and V_OA1.

Figure 11 The schematic shows a simplified circuit for V_IA1 and V_OA1. Source: Texas Instruments

Equation 2 calculates V_IA1:

The analysis for V_OA1 simplifies by applying the input-virtual-short property of ideal op amps. The voltage that appears at the R_G pin connected to the inverting terminal of A2 is the same as the voltage at V_+IN. Superposition results are shown in Equation 3, which simplifies to Equation 4.

Applying a similar analysis to A2 (Figure 12) yields Equation 5, Equation 6 and Equation 7.

Figure 12 This is a simplified circuit for V_IA2 and V_OA2. Source: Texas Instruments

Difference amplifier output stage

Figure 13 shows that A3, R₁ and R₂ make up the difference amplifier output stage, whose transfer function is defined in Equation 8.

Figure 13 The above schematic displays difference amplifier input (V_DIFF). Source: Texas Instruments

Equation 9, Equation 10 and Equation 11 use the equations for V_OA1 and V_OA2 to derive V_DIFF in terms of the differential input signal, V_D, as well as R_F and the gain-setting resistor, R_G.

Substituting Equation 11 for V_DIFF in Equation 8 yields Equation 12, which is the same as Equation 1.

In most IAs, the gain of the output stage is 1 V/V. If the gain of the output stage is 1 V/V, Equation 12 simplifies to Equation 13:

Figure 14 determines the equations for nodes V_OA3 and V_IA3.

Figure 14 This diagram highlights difference amplifier internal nodes. Source: Texas Instruments

The equation for V_OA3 is the same as V_OUT, as shown in Equation 14:

Using superposition as shown in Equation 15 determines the equation for V_IA3. The voltage at the non-inverting node of A3 sets the amplifier’s common-mode voltage. Therefore, only V_OA2 and V_REF affect V_IA3.

Since G_OS=R₂/R₁, Equation 15 can be rewritten as Equation 16:

Part 2 highlights

The second part of this series will use the equations from the first part to plot each internal amplifier’s input common-mode and output-swing limitation as a function of the IA’s common-mode voltage.

Peter Semig is an applications manager in the Precision Signal Conditioning group at Texas Instruments (TI). He received his bachelor’s and master’s degrees in electrical engineering from Michigan State University in East Lansing, Michigan.

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